Parallel/serial conversion circuit, light output control circuit, and optical recording apparatus

ABSTRACT

A high speed, high accuracy parallel/serial conversion circuit, wherein a PLL circuit  50  receives as input and locks a clock CLK, and supplies the same to different parts of an apparatus; the PLL circuit  50  controls a 16-tap ring oscillator  60  to shift the phase of a clock frequency-locked to a reference clock so as to generate 32 types of phase shift pulses CK 0  to CK 31  shifted in phase by increments of {fraction (1/32)} of the clock width from the reference clock by the differential outputs of the 16 taps and supplies the same to a P/S conversion circuit  70 ; and the P/S conversion circuit  70  generates fine width pulses with {fraction (1/32)} pulse widths based on the 32 types of phase shift pulses shifted in phase by increments of {fraction (1/32)}. Further, the fine width pulses are used to convert parallel signals output from a RAM  30  and a decoder  40  to a serial signal.

TECHNICAL FIELD

The present invention relates to a parallel/serial conversion circuitfor converting parallel signal input to a serial pulse signal andoutputting the same, a light output control circuit for controlling alight output from a light source for emitting various types ofinformation to a rewritable optical recording medium, etc., such as aphase change type optical disk, and an optical recording apparatus.

BACKGROUND ART

In recent years, advances have been made in increasing the speeds of avariety of electronic apparatuses. For example, in an optical recordingapparatus for writing information on an optical disk, an increase in thespeed of the conversion operation is being sought for theparallel/serial conversion circuit (hereinafter called the “P/Scircuit”) that converts the recording data from parallel signals to aserial signal and outputs the results to a laser driver.

However, when trying to increase the speed of the conversion operationin a P/S circuit, since the serial signal after parallel/signalconversion becomes a super high speed, a super high speed clock isrequired for outputting the serial signal. Increasing the speed of theclock ends up creating obstacles in technology and cost.

DISCLOSURE OF THE INVENTION

A first object of the present invention is to provide a parallel/serialconversion circuit able to realize higher speed and higher accuracy at alow cost without using a super high speed clock.

A second object of the present invention is to provide a light outputcontrol circuit and an optical recording apparatus using thisparallel/serial conversion circuit to optimize waveform control of aserial output pulse signal with a high speed and a high accuracy.

To achieve the objects, a first aspect of the present invention is aparallel/serial conversion circuit for converting parallel signals inputto a serial pulse signal and outputting the same, having a phaseshifting means for shifting a phase of a reference clock pulse byincrements of 1/n width of a pulse width, a fine width pulse generatingmeans for receiving as input two phase shift pulses among the phaseshift pulses shifted by the phase shifting means and generating a finewidth pulse from a phase difference between the two, and a serial signalgenerating means for serially adding the fine width pulses generated bythe fine width pulse generating means corresponding to the parallelsignal input and outputting a serial pulse signal.

A second aspect of the present invention is a light output controlcircuit which controls a light output of a light source for emittingpredetermined data light to an optical medium, having a light sourcedriver that drives the light source in response to the serial pulsesignal and a parallel/serial conversion circuit which receives as inputparallel signals based on waveform data corresponding to light data tobe emitted by the light source, converts the parallel signals to aserial pulse signal, and outputs the same to the light source driver,the parallel/serial conversion circuit having a phase shifting means forshifting a phase of a reference clock pulse by increments of 1/n widthof a pulse width, a fine width pulse generating means for receiving asinput two phase shift pulses among the phase shift pulses shifted by thephase shifting means and generating a fine width pulse from a phasedifference between the two, and a serial signal generating means forserially adding the fine width pulses generated by the fine width pulsegenerating means corresponding to the parallel signal input andoutputting a serial pulse signal.

Preferably, it further has a waveform data memory for storing waveformdata corresponding to data to be emitted by the light source, anaccessing means for receiving as input the data to be emitted by thelight source, judging the address of the waveform data memorycorresponding to the input data, and accessing the waveform data memory,and a decoding means for decoding the waveform data read from thewaveform data memory by the accessing means and outputting parallelsignals which indicate the pulse waveform data to a parallel/serialconversion circuit.

Further, preferably, the fine width pulse generating means generates thefine width pulse from two adjacent phase shift pulses among the phaseshifted pulses shifted by the phase shifting means.

Further, it has a changing means for receiving as input two adjacentphase shift pulses among the phase shift pulses shifted by the phaseshifting means and changing their levels to different levels; and thefine width pulse generating means generates the fine width pulse fromthe two phase shift pulses changed in level by the level changing means.

Further, in the present invention, the phase shifting means includes aring oscillator connecting a plurality of cells in a ring.

Preferably, the phase shifting means includes a ring oscillatorconnecting a plurality of delay cells in a ring, and the plurality ofdelay cells are laid out so as to make delays cells which becomeodd-numbered stages and even-numbered stages when connected in a ringface each other and so that interconnects which connect them becomeapproximately equal.

A third aspect of the present invention is an optical recordingapparatus for outputting a light source drive signal to a light sourcedriver which writes data to an optical recording medium based onrecording data indicating a length of a mark to be recorded on theoptical recording medium, having a parallel/serial conversion circuitfor receiving as input parallel signals based on waveform data read froma waveform data memory corresponding to a length of a mark recorded onthe optical recording medium, converting the parallel signals to aserial pulse signal, and outputting the same to the light source driver,the parallel/serial conversion circuit having a phase shifting means forshifting a phase of a reference clock pulse by increments of 1/n widthof the pulse width, a fine width pulse generating means for receiving asinput two phase shift pulses among the phase shift pulses shifted by thephase shifting means and generating a fine width pulse based on a phasedifference between the two, and a serial signal generating means forserially adding the fine width pulses generated by the fine width pulsegenerating means corresponding to the parallel signal input andoutputting a serial pulse signal.

According to the parallel/serial conversion circuit of the presentinvention, since it shifts a phase of a reference clock pulse byincrements of 1/n width of the pulse width, generates a fine width pulsefrom the phase difference between two phase shift pulses among the phaseshift pulses, serially adds the fine width pulses corresponding to theparallel signal input, and outputs a serial pulse signal, it is possibleto realize a higher speed and a higher accuracy of the P/S conversion ata low cost without using a super high speed clock.

Further, according to the present invention, when receiving as inputparallel signals based on waveform data read from a waveform data memorycorresponding to a length of a mark to be recorded on an opticalrecording media and converting these parallel signals to a serial signalby a parallel/serial conversion circuit and outputting the same to alight driver, since it shifts the phase of a reference clock pulse byincrements of 1/n width of the pulse width, generates a fine width pulsefrom the phase difference between two phase shift pulses among the phaseshift pulses, serially adds the fine width pulses corresponding to theparallel signal input, and outputs a serial pulse signal, it is possibleto realize a higher speed and a higher accuracy of P/S conversion at alow cost without using a super high speed clock and optimize waveformcontrol of a pulse signal output to a light source driver for high speedand high accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of a light output controlcircuit according to the present invention.

FIGS. 2(A) to (D) are views for explaining a reference clock and a lightdrive pulse signal used in a light driver shown in FIG. 1.

FIG. 3 is a view for explaining the functions of mode registers.

FIGS. 4(A) to (C) are views for explaining data in a serial interfaceaccording to the present embodiment.

FIGS. 5(A) to (H) are views for explaining recording data, that is,parallel data, in the present embodiment.

FIG. 6 is a view of an array of RAM data at the time of a first strategymode.

FIG. 7 is a view of an array of RAM data at the time of a secondstrategy mode.

FIGS. 8(A) to (H) are views of an example of the configuration of datain a first strategy mode.

FIGS. 9(A) to (H) are views of an example of the configuration of datain a second strategy mode.

FIG. 10 is a view of an example of the layout for delay cells forming a16-tap ring oscillator according to the present embodiment.

FIG. 11 is a view of a concrete example of the configuration of the16-tap ring oscillator according to the present embodiment.

FIG. 12 is a block diagram of the configuration of a P/S conversioncircuit of an optical recording apparatus shown in FIG. 1.

FIGS. 13(A) and (B) are explanatory views of an example of a serialsignal comprised of fine width pulses serially connected and output inthe P/S conversion circuit shown in FIG. 12.

FIG. 14 is a block diagram of the circuit configuration of an MEL switchcircuit provided in the P/S conversion circuit shown in FIG. 12.

FIGS. 15(A) and (B) are views for explaining signal processing contentin the MEL switch circuit shown in FIG. 14.

FIG. 16 is a circuit diagram of a detailed example of the configurationof the MEL switch circuit and its peripheral circuits.

FIG. 17 is a view of a level-changed clock waveform.

FIG. 18 is a circuit diagram of a concrete example of the configurationof a clock driver in FIG. 16.

FIGS. 19(A) to (L) are timing charts of processing for generating thefine width pulses in the P/S conversion circuit shown in 16.

FIG. 20 is a circuit diagram of principal parts of an optical diskapparatus as an optical recording apparatus employing the light outputcontrol circuit according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Below, an embodiment of the present invention will be explained indetail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a light output controlcircuit according to the present invention.

The present light output control circuit 1 has, as shown in FIG. 1, amode register (MREG) unit 10, an address encoder (AENC) 20, a RAM(waveform data memory) 30, a decoder (DEC) 40, a PLL (Phase Locked Loop)circuit 50, a 16-tap ring oscillator (OSC) 60 as a phase shifting means,a parallel/serial (P/S) conversion circuit 70, an output circuit (OUTC)80, a light source driver (LDDRV) 90, and a laser light source (LD) 100.

Among these components, the mode register unit 10, the address encoder20, the RAM 30, the decoder 40, the PLL circuit 50, the 16-tap ringoscillator 60, the P/S conversion circuit 70, and the output circuit 80constitute a pulse signal generation circuit.

Further, in the circuit shown in FIG. 1, the PLL circuit 50, the 16-tapring oscillator 60, the P/S conversion circuit 70, and the outputcircuit 80 constitute a super high-speed bipolar transistor circuit A,which realizes a 5 GHz operation for the above-mentioned high-speeddrive, and the other portions constitute a MOS-type circuit by CMOScircuits, etc. Further, the super high-speed bipolar transistor circuitA forms the parallel/serial conversion circuit according to the presentinvention.

Furthermore, the light output control circuit 1 is, for example, usedfor a phase change type optical disk apparatus or the like of arewritable optical disk system, increasing in use in recent years.

This phase change type optical disk requires optimization of the pulsewaveform of the write pulse for controlling the laser power. Thismodified control of a write pulse is called a “write strategy”.

Therefore, in the present embodiment, an explanation will be giventaking as an example, particularly, a circuit suitable for a writestrategy which converts to a light drive signal consisting of a pulsestring having fine widths by three levels in response to a record marklength.

First, prior to an explanation of the configurations and functions ofthe components in the circuit, the light drive signal of the laser lightsource 100 from the light source driver 90 will be explained.

FIGS. 2(A) to (C) are views for explaining a reference clock used in thelight driver 90 and a pulse signal for light drive use. FIG. 2(A) showsa reference clock (channel clock) RCLK (CCLK); FIG. 2(B) shows a recordmark RMK; and FIG. 2(C) shows a drive current Iop of the laser lightsource (LD) 100.

First, in the present example, 1-7 modulation is used as a lightmodulation scheme, 2T to 8T are used as mark lengths, and 2T to 8T areused as space lengths. Here, T is the period of the channel clock.

Here, assuming th e reference clock (channel clock) RCLK (CCLK) shown inFIG. 2(A) is, for example, 66 MHz, 1T becomes 15 nsec.

When recording a mark, write pulses of a number and waveform set foreach mark length are output. These write pulses drive the laser lightsource 100 and control the quantity of heat.

Further, the laser power of the laser light source 100 used in thepresent example has three values, that is, an erase level (Erase) wherethe light strikes a space portion of the optical disk medium, a coollevel (Cool) where it melts the recording layer to create an amorphousmark, and a peak level (Peak).

The drive current lop is a maximum 200 mA at the peak level (Peak) andabout 40 mA at the cool level (Cool), and drives between the cool level(Cool) and the peak level (Peak) by a 1 ns rising edge time/falling edgetime.

Further, the light source driver 90 for actual recording by thethree-value laser power has an APC (automatic power control) circuit forfeedback control.

The drive current lop for driving the laser light source 100, that is,the write pulse, becomes, for example, the waveform shown in FIG. 2(C).

That is, the operation for recording a 5T mark is controlled using thetimings of a total of seven pulses comprised of five pulsescorresponding to 5T of reference clocks RCLK and one pulse each frombefore and after them. In the waveform, after an erase level (Erase),four write pulses repeating a cool level (Cool) and a peak level (Peak)are output, and then the cool level (Cool) is returned to the eraselevel (Erase).

Further, the operation for recording a 2T mark is controlled by thetimings of a total of four pulses comprised of two pulses correspondingto 2T of reference clocks RCLK and one pulse each from before and afterthem. In the waveform, after an erase level (Erase), one write pulserepeating a cool level (Cool) and a peak level (Peak) is output, andthen the cool level (Cool) is returned to the erase level (Erase).

The light output control circuit 1 in the present embodiment generatesthe above-mentioned, light source drive signal in a state optimizing thepulse waveform (write strategy). It sets the waveform data for obtainingthe above-mentioned, light source drive signal, generates pulse signalswith rising edges and falling edges independently controlled by thewaveform data, and supplies the same to a later light-source driver 90.

Note that the targeted accuracy in the circuit of the present examplehas, for example, made the pulse edge timing about 500 psec to 200 psec.

Therefore, to satisfy this requirement, an integrated circuit (IC) setsa total of eight systems of outputs, including four systems with a{fraction (1/32)}T accuracy corresponding to a 200 pS resolution and 4systems with a ¼T accuracy. Further, the IC uses a RAM 30 of asufficient capacity for storing 50 types of independent parameters forthe respective eight systems and uses a bipolar transistor circuit A forhigh-speed drive in its circuit configuration.

Next, the configurations and the functions of the components in FIG. 1will be explained in order with reference to the drawings.

The register unit 10 is comprised of a group of registers forregistering setting data from the outside to the RAM 30 or the like viaa serial interface, and it is used at a different setting mode from thenormal operation.

Particularly, in the present example, it is necessary to store the laterexplained waveform data in the RAM 30. The waveform data are writtenfrom the register unit 10 to the RAM 30 by using a write clock WCLK anda write address Wadr.

The register unit 10 has, for example, eight mode registers (MREG0 toMREG7) for setting modes. The mode registers MREG0 to MREG7 have, forexample, the functions as shown in FIG. 3.

The mode register MREG0 is a register for setting page address datashowing a sub-address of the RAM. The mode register MREG1 is a registerfor setting data for power saving control for the channel of not shownoutput ports. The mode register MREG2 is a register for power saving ofa chip. The mode register MREG3 is a register for setting a lock rangeof a PPL circuit 50 and selecting an operation mode and a number ofinput channels. The mode register MREG4 is a register for setting datato select a test mode, a strategy mode, and an output power mode. Themode register MREG5 is a register for setting data to switch on or off amonitor output. The mode register MREG6 is a register for setting datato control a write gate (WG) and a WG timer. The mode register MREG7 isa register for setting data to set a mode that lowers a PLL operationfrequency and operates the PLL at a low frequency.

The addresses of the mode registers MREG0 to MREG7 are, as shown in FIG.3 allocated as 00h to 07h (h indicates hexadecimal number).

Data to set the mode registers MREG0 to MREG7 are supplied to the moderegister unit 10 via a serial interface.

The serial interface includes, for example, as shown in FIGS. 4(A) to(C), three signals, that is, a chip select XCS, a serial clock SCLK, anda serial data SDI signal.

The mode register unit 10, as shown in FIGS. 4(A) to C), fetches serialdata SDI from the least significant bit (LSB) at the rising edge of theserial clock SCLK and sets the same to a predetermined mode registerMREG at the rising edge of the chip select XCS.

Further, as shown in FIG. 4(C), in the serial data SDI, the address bitsare A0 to A5, the bit A6 is a register/RAM selection bit, and the bit A7is a write(WR)/read(RD) selection bit.

For example, by setting the bit A7 to “H” (high level) and setting thebit A6 to “H” to set the bit A5 to “L” (low level) in the register, itis possible to write data in the RAM.

Note that when reading data from the RAM and when writing data in theRAM, it is necessary to write a page address in the mode register MREG0in advance.

The address encoder 20, at the time of a normal recording operation,receives as input the recording data (NRZI), for example, the paralleldata signals DT0 to DT5 shown in FIGS. 5(A) to (H), converts it toserial data at the rising edge timing of the clock signal DCLK, judgesthe converted recording data (2T˜≧8T or 2T˜≧4T), generates a readaddress Radr of the RAM 30 in which is written a pulse patterncorresponding to a mark length and a space length shown by the recordingdata, outputs the same with a read clock RCLK to the RAM 30, and makesthe RAM 30 execute a read operation of the waveform data.

The RAM 30 serving as a waveform data memory stores waveform datacomprised by a number of strings of pulse waveform data corresponding tothe mark length of the light source drive signal, searches through amemory area based on a read address received from an address encoder 20,and outputs the corresponding waveform data to the decoder 40.

As the method of using the RAM, there are two types of strategy modes,that is, a first strategy mode able to set a pulse pattern of a 2T˜≧8Tmark length and a second strategy mode able to set a pulse pattern of a2T˜≧4T mark length.

FIG. 6 is a view of an array of RAM data at the time of the firststrategy mode, while FIG. 7 is a view of an array of RAM data at thetime of the second strategy mode.

In the first strategy mode, it is possible to output any waveform datafor a 2T˜≧8T mark length. As shown in FIG. 6, waveform datacorresponding to 2T˜≧8T are written into every channel CH1 to CH4.

Further, in the second strategy mode, it is possible to output anywaveform data for a 2T˜≧4T mark length. As shown in FIG. 7, the numberof pulse patterns which can be set becomes half, but it is possible towrite two types of pulse patterns for every channel CH1 to CH4 and toreduce th e communication time by writing data in the RAM beforehand.

Further, as shown in FIG. 6 and FIG. 7, page address data PAD isdesignated by the lower 3 bit s of th e mode register MREG0 in the moderegister unit 10.

FIGS. 8(A) to (H) are views of an example of the data configuration inthe first strategy mode, and FIGS. 9(A) to (H) are views of an exampleof the t data configuration in the second strategy mode.

In FIGS. 8(A) to (G) and FIGS. 9(A) to (G), LA1 indicates “Leading Area1”, LA2 indicates “Leading Area 2”, PoLA indicates “Post Leading Area”,CA indicates “Central Area”, PrTA indicates “Pre Trailing Area”, TA1indicates “Trailing Area 1”, and TA2 indicates “Trailing Area 2”.

In the waveform data in the present example, two to eight strings ofpulse waveform data are allocated for a 2T to 8T mark length and onestring each of waveform data is allocated before and after the same toform the waveform data for each mark length. That is, for example, ifthe mark length is 2T, four strings of pulse waveform data and if themark length is 5T, seven strings of pulse waveform data are used to formthe waveform data.

In FIGS. 8(A) to (C) and FIGS. 9(A) to (C), the portion where thewaveform is “H” shows pulse waveform data for the mark length.

Further, the notations attached to the pulse waveform data for the marklength and pulse waveform data before and after the same show individualsetting data set for the pulse waveform data.

For example, the notations “2TLA2” and “2T TA1” are attached in order tothe two strings of pulse waveform data forming a 2T mark length and thenotations “2T LA1” and “2T TA2” are attached in order before and afterthe pulse waveform data.

Further, the notations “3T LA2”, “2T PoLA”, and “3T TA1” are attached inorder to three strings of pulse waveform data forming a 3T mark lengthand the notations “3T LA1” and “3T TA2” are attached in order before andafter the pulse waveform data.

It is shown that pulse waveform data differentiated by these notationshave unique setting data.

Note that identical notations show pulse waveform data of identicalcontents. In particular, long mark length data have a structurerepeatedly using identical data “6T CA” and “7T CA” at the middle partof the mark.

Further, each waveform data is configured to specify each pulse waveformby data of the rising edge position and falling edge position and thepolarity.

For example, as shown in FIG. 6, each pulse waveform is specified bywriting the first edge data and the second edge data to reach area.

Here, the rising edge position and the falling edge position, whenexpressing the maximum pulse width by n number of bits, are dataspecifying the rising edge bit and the falling edge bit among the nbits. For example, when using a resolution where the maximum pulse widthcan be represented by 32 bits, one bit among the 32 bits is specified toshow the position of the rising edge position or the falling edgeposition of the pulse signal. 32 bits of data can be expressed by 5 bitsof binary data at each of the rising edge position and falling edgeposition.

Further, the polarity of the pulse signal is represented by one bit ofbinary data.

Therefore, in this case, each pulse waveform data is comprised of 5bits+5 bits+1 data.

Such 11 bit-configuration waveform data are set in the memory areasallocated to the above notations “2T LA1” and “2T LA2”.

The post leading area PoLA is present as an area in data of 3T or more,the pre-trailing area PrTA in 4T or more, and the central area CA in 5Tor more. The central areas CA are increased one by one for 6T or more.

Further, as described above, the first strategy mode shown in FIG. 8 andthe second strategy mode shown in FIG. 9 have different contents formark lengths of 4T or more.

That is, in the first strategy mode shown in FIG. 8, waveform data areindividually set for all mark lengths from 2T to 8T. A larger memoryspace is used to store the waveform data.

Since waveform data are set individually for all mark lengths from 2T to8T, the drive of the LD light source 100 is controlled more finely.

On the other hand, in the second strategy mode shown in FIG. 9, thewaveform data used for a 4T mark length are applied for mark lengths of5T or more.

That is, waveform data expressed by the notations “≧4T LA1” and “≧4TLA2” allocated for the 4T mark length are utilized as is for waveformdata of mark lengths of 5T or more. Namely, the notation “≧” attached atthe head of each notation means use in common for waveform data of 4T ormore.

By using the second strategy mode shown in FIG. 9, it is possible toconserve the memory area in the RAM 30.

Further, for example, in the case of an optical recording medium of astructure recording data by both lands and grooves, sometimes theoptimal light source drive signal differs between the lands and thegrooves. It becomes necessary to set the waveform data individually.Therefore, by using the second strategy mode shown in FIG. 9 to setdifferent waveform data at the time of recording on the lands and at thetime of recording on the grooves, it becomes possible to use anequivalent memory area as the case of the first strategy mode forcontrol of the light source optimized for both land recording and grooverecording.

The decoder (DEC) 40 converts the waveform data read from the RAM 30 toa pulse signal of parallel two-value data corresponding to the pulsewaveforms.

For example, when the resolution can express a pulse width by 32 bits,if the polarity is positive, a parallel pulse signal having the bitsfrom the head bit to the rising edge bit indicated by the pulse waveformdata as “L”, the bits from the rising edge bit to the falling edge bitas “L”, and the bits from the falling edge bit to the last bit as “L” isoutput, while conversely if the polarity is negative, a parallel pulsesignal having the bits from the head bit to the rising edge bitindicated by the pulse waveform data as “H”, the bits from the risingedge bit to the falling edge bit as “L”, and the bits from the fallingedge bit to the last bit as “H” is output.

Note that up to here, the operation was based on the reference clock(channel clock) RCLK (CCLK).

The PLL circuit 50, for example, generates a clock signal synchronizedin phase to a synchronization signal DCLK of the parallel signals DT0 toDT5 input to the address decoder 20 and supplies it to the 16-tap ringoscillator 60. The PLL circuit 50 includes a VCO (voltage controlledoscillator). For example, when six parallel signals are input asmentioned above, the VCO oscillates by 6 times the input frequency.Further, the PLL circuit 50 can be set in the lock range correspondingto the operation frequency.

The 16-tap ring oscillator 60 shifts the phase of the clock generated bythe PLL circuit 50 and synchronized in phase to a reference clock so asto generate 32 types of phase shift pulse signals CK0 to CK31 shifted inphase by increments of {fraction (1/32)} (1/n) of the clock width fromthe reference clock by the differential outputs of the 16 taps andoutputs these phase shift pulse signals CK0 to CK31 to the P/Sconversion circuit 70. The pulse signal CK0 is supplied via a buffer BUFto the address encoder 20, the RAM 30, and the decoder 40.

The 16-tap ring oscillator has, for example as shown in FIG. 10, 16delay cells DC0 to DC15. In the present embodiment, to equalize thedelay steps (equalize the interconnects), the layout shown in FIG. 10 isapplied.

Concretely, as shown in FIG. 10, eight cells each are equally arrangedin two stages. In the figure, the top stage has the even numberednotation delay cells DC12, DC4, D14, DC6, DC10, DC2, DC0, and DC8arranged from the left side at substantially equal intervals, while thebottom stage has the odd numbered notation delay cells DC13, DC5, D11,DC3, DC15, DC7, DC9, and DC1 arranged from the left side atsubstantially equal intervals. The cells are connected by interconnectsin order from DC0 to DC15. As a result, a ring-shaped oscillator isrealized.

The delay cells DC0 to DC15 are differential type oscillators. The delaycells DC0 to DC15 output 32 types of phase shift pulses shifted in phaseby increments of {fraction (1/32)}.

FIG. 11 is a circuit diagram of the concrete configuration of a delaycell DC (0 to 15) according to the present embodiment.

The delay cell DC has a cascade-connected delay controller 61, a mixedamplifier 62, and an output portion 63.

The delay controller 61 has npn-transistors Q611 to Q614, variablecurrent sources I611 and I612, diodes D611 to D614, and capacitors C611and C612.

Emitters of the transistors Q611 and Q612 are connected, and theconnection point is connected to the current source I611. Emitters ofthe transistors Q613 and Q614 are connected, and the connection point isconnected to the current source I612. Bases of the transistor Q611 andQ614 are connected to an input line of a clock DCLK, and bases of thetransistors Q612 and Q613 are connected to an input line of a clock CKK.

A collector of the transistor Q611 is connected to a first electrode ofthe capacitor C611 and a cathode of the diode D611, while a secondelectrode of the capacitor C611 and an anode of the diode D611 areconnected to a supply line of a power supply voltage V_(DD). A collectorof the transistor Q612 is connected to a first electrode of thecapacitor C612 and a cathode of the diode D612, while a second electrodeof the capacitor C612 and an anode of the diode D612 are connected tothe supply line of the power supply voltage V_(DD). A collector of thetransistor Q613 is connected to a cathode of the diode D613, while ananode of the diode D613 is connected to the supply line of the powersupply voltage V_(DD). A collector of the transistor Q614 is connectedto an cathode of the diode D614, while an anode of the diode D614 isconnected to the supply line of the power supply voltage V_(DD).

The delay controller 61 is configured so that it can control the amountof delay by controlling the current I_(VCO) of the current sources I611and I612 with a control signal CTLI.

The mixed amplifier 62 has npn-transistors Q621 to Q624, current sourcesI621 and I622, and resistors R621 and R622.

Emitters of the transistors Q621 and Q622 are connected, and theconnection point is connected to the current source 1621. Emitters ofthe transistors Q623 and Q624 are connected, and the connection point isconnected to the current source I622.

A base of the transistor Q621 is connected to a collector of thetransistor Q612, a base of the transistor Q622 is connected to acollector of the transistor Q611, a base of the transistor Q623 isconnected to a collector of the transistor Q614, and a base of thetransistor Q624 is connected to a collector of the transistor Q613.

Further, the collectors of the transistors Q621 and Q624 are connected,and the connection point is connected to the supply line of the powersupply voltage V_(DD) via the resistor R612.

That is, the mixed amplifier amplifies four differential outputs of thedelay controller 61, mixes the same two by two, and supplies the resultsto the output portion 63.

In the mixed amplifier 62, a ratio between a current I1 of the currentsource I621 and a current I2 of the current source I622 is set toI1:I2=1:1 or I1:I2=0.4:1.6 etc. A higher band of the control range isrealized by switching the mixing ratios.

The output portion 63 has npn-transistors Q631 and Q632 and currentsources I631 and I632.

A base of the transistor Q631 is connected to collectors of thetransistors Q621 and Q624, a collector is connected to the supply lineof the power supply voltage V_(DD), an emitter is connected to thecurrent source I631, and the connection point is connected to an outputterminal Tout1. A base of the transistor Q632 is connected to collectorsof the transistors Q622 and Q623, a collector is connected to the supplyline of the power supply voltage V_(DD), an emitter is connected to thecurrent source I632, and the connection point is connected to an outputterminal Tout2.

That is, the output portion 63 has an emitter-follower output stageconfiguration.

The P/S conversion circuit 70 generates a fine width pulse from thephase difference of two phase shift pulses among the phase shift pulsesCK0 to CK31 shifted by the oscillator 60 based on the two pulses,converts the generated plurality of fine width pulses to a serial pulsesignal by serially adding the parallel two-value signals from thedecoder 40, and outputs the same to the output circuit 80.

Further, the output circuit 80 performs necessary processing such asamplification and impedance matching on the serial signal from the P/Sconversion circuit 70 and outputs the result to the light source driver90.

Note that, in the present embodiment, as mentioned above, there areeight systems of output.

This is because, for example, a plurality of systems is provided in theconfiguration from the RAM 30 on so as to generate separately pulsesignals with different levels such as an erase level (Erase) and a peaklevel (Peak) shown in FIG. 2 and mix them at the later light sourcedriver 90 or so as to perform waveform processing of a lower resolutionthan the above 32-bit resolution. These are suitably selected and used.

The P/S conversion circuit 70 prepares fine width pulses having{fraction (1/32)} pulse widths based on such 32 types of phase shiftpulses shifted in phase by increments of {fraction (1/32)} and uses thefine width pulses to convert parallel signals to a serial signal.

FIG. 12 is a block diagram of the configuration of the P/S conversioncircuit according to the present embodiment.

As shown in FIG. 12, the P/S conversion circuit 70 has 32 MEL(multi-level emitter logic) switch circuits SW1 to SW32 and an adder SA(sense amplifier) which adds the outputs from the MEL switch circuitsSW1 to SW32.

The MEL switch circuits SW1 to SW32 receive as input two adjacent phaseshift pulses (for example, CK0 and CK1, CK1 and CK2, CK2 and CK3, . . .) among the phase shift pulses CK0 to CK31 and obtain the differences ofthe two phase shift pulses so as to output the above-mentioned {fraction(1/32)} fine width pulses.

Further, two outputs are prepared for the outputs of the MEL switchcircuits SW1 to SW32. In accordance with the above-mentioned pulsewaveform data, fine width pulses are selectively output to a positivepolarity input side (+) or a negative polarity input side (−) of theadder SA. These fine width pulses are added by the adder SA where thefine width pulses are serially connected, whereby a serial signalcorresponding to the pulse waveform data is output.

FIG. 13 is an explanatory view of an example of a serial signal obtainedby serially connecting these fine width pulses.

The example illustrated, as shown in FIG. 13(B), shows a case in whichseven fine width pulses are output from a third MEL switch circuit SW3to a ninth MEL switch circuit SW9 to the positive polarity input side ofthe adder SA. These successive seven fine width pulses are seriallyadded by the adder SA. As shown in FIG. 13(A), a positive polarity pulsewaveform signal having a pulse width {fraction (7/32)}T which rises at atiming of {fraction (3/32)}T and falls at a timing of {fraction(10/32)}T is output.

FIG. 14 is a block diagram of the circuit configuration of a MEL switchcircuit, while FIG. 9 is an explanatory view of the content of thesignal processing in a MEL switch circuit.

As shown in FIG. 14, the MEL switch circuit has two differentialamplifiers comprised of pairs of npn-transistors Q71, Q72 and Q73, Q74,a constant current source 171 connected in common to the emitters of thetransistors Q71, Q72, Q73, and Q74, and NMOS-transistors Q75 and Q76selectively connecting either of the two differential amplifiers to theconstant current source 171 in accordance to the above-mentionedwaveform data (DATA).

Among the above-mentioned two phase shift pulses CKn and CKn+1, thephase shift pulse CKn is supplied to the bases of the transistors Q71and Q74 of the differential amplifers, while the phase shift pulse CKn+1is supplied to the bases of the transistors Q72 and Q73 of the twodifferential amplifiers.

The phase shift pulses CKn and CKn+1 are, as shown in FIG. 15(B),changed in level by a later explained buffer circuit provided at theinput stage and are input as phase shift pulses having a constant leveldifference from each other.

Further, the transistors Q71 and Q72 of one differential amplifiersubtract the low-level phase shift pulse CKn from the high-level phaseshift pulse CKn+1, whereby a fine width pulse due to the leveldifference (200 psec pulse width in the example of FIG. 14(A)) is outputas the collector current IP of the transistor Q71.

Further, the transistors Q73 and Q74 of the other differentialamplifier, like the transistors Q71 and Q72, subtract the low-levelphase shift pulse CKn from the high-level phase shift pulse CKn+1,whereby a fine width pulse due to the level difference is output as thecollector current IP of the transistor Q74.

Further, either of the MOS transistors Q75 and Q76 turns on based on thewaveform data (including polarity data) from the decoder 40. Byconnecting either differential amplifier to the constant current sourceI, the operations of the differential amplifiers are executedselectively corresponding to the waveform data.

FIG. 16 is a circuit diagram of a detailed example of the configurationof a MEL switch circuit and its peripheral circuits.

In the figure, the transistors Q71 to Q76, the current source I71, etc.of the above-mentioned MEL switch circuit are provided in a selector110. The selector 110 is provided around it with a clock driver 120, ashift register 130, a buffer 140, etc. Note that the selector 110 hasMOS transistors Q77 to Q82 for conveying data to the MOS transistors Q75and Q76 at predetermined levels connected serially and/or in parallelbetween the supply line of the power supply voltage V_(DD) and thereference potential V_(SS) and is configured so that a signal of thepower supply voltage V_(DD) level or reference potential level issupplied to the gates of the MOS transistors Q75 and Q76.

The output line is provided with the sense amplifier 150 forming theadder SA. The output signal from the sense amplifier 150 is sent to anECL output amplifier 160 of the output circuit 80.

The clock driver 120 has, as shown in FIG. 16, operational amplifiersOP121 to OP123. It receives the above-mentioned phase shift pulses atthe operational amplifier OP121, converts them in level at theoperational amplifiers OP122 and OP123 as shown in FIG. 17, and suppliesthe results to the selector 110.

FIG. 18 is a circuit diagram of a concrete example of the configurationof the clock driver 120.

The clock driver 120, as shown in FIG. 18, has npn-transistors Q1201 toQ1221 and resistors R1201 to R1216.

Emitters of the transistors Q1201 and Q1202 are connected, theconnection point is connected to a collector of the transistor Q1209serving as a current source, and an emitter of the transistor Q1209 isgrounded via the resistor R1209. A collector of the transistor Q1201 isconnected to the supply line of the power supply voltage V_(CC) via theresistor R1201 and is connected to a base of the transistor Q1207.Further, a collector of the transistor Q1207 is connected to the supplyline of the power supply voltage V_(CC), an emitter is connected to thebases of the transistors Q1203 and Q1205 and a collector of thetransistor Q121 serving as a current source, and an emitter of thetransistor Q1212 is grounded via the resistor R1208. A collector of thetransistor Q1202 is connected to the supply line of the power supplyvoltage V_(CC) via the resistor R1205 and is connected to the base ofthe transistor Q1208. Further, a collector of Q1208 is connected to thesupply line of the power supply voltage V_(CC), an emitter is connectedto bases of the transistors Q1204 and Q1206 and is connected to acollector of the transistor Q1213 serving as a current source, and anemitter of the transistor Q1213 is grounded via the resistor R1212.Further, a base of the transistor Q1209 serving as a current source isconnected to the supply line of a control signal C1201, and bases of thetransistors Q1212 and Q1213 similarly serving as current sources areconnected to a supply line of a control signal C1202.

Further, a base of the transistor Q1201 is connected to an input line ofthe phase shift clock CK, and a base of the transistor Q1202 isconnected to an input line of the phase shift clock XCK.

The transistors Q1201, Q1202, Q1209, Q1212, and Q1213 and the resistorsR1201, R1205, R1208, R1209, and R1212 constitute the input stageoperational amplifier OP121.

Emitters of the transistors Q1203 and Q1204 are connected, theconnection point is connected to a collector of the transistor Q1211serving as a current source, and an emitter of the transistor Q1211 isgrounded via the resistor R1211. A collector of the transistor Q1203 isconnected to the supply line of the power supply voltage V_(CC) via theresistor R1202 and connected to the base of the transistor Q1215.Further, a collector of the transistor Q1215 is connected to the supplyline of the power supply voltage V_(CC), an emitter is connected to acollector of the transistor Q1219 serving as a current source, and anemitter of a transistor Q1219 is grounded via the resistor R1214. Acollector of the transistor Q1204 is connected to the supply line of thepower supply voltage V_(CC) via the resistor R1204 and is connected to abase of the transistor Q1214. Further, a collector of Q1214 is connectedto the supply line of the power supply voltage V_(CC), an emitter isconnected to a collector of the transistor Q1218 serving as a currentsource, and an emitter of the transistor Q1218 is grounded via theresistor R1213. Further, a base of the transistor Q1211 serving as acurrent source is connected to a supply line of a control signal C1202and bases of the transistors Q1218 and Q1219 similarly serving ascurrent sources are connected to a supply line of a control signalC1203.

The transistors Q1203, Q1204, Q1211, Q1214, and Q1215 and the resistorsR1202, R1204, R1211, R1213, and R1214 constitute the high level outputstage operational amplifier OP122.

Emitters of the transistors Q1205 and Q1206 are connected, theconnection point is connected to a collector of the transistor Q1210serving as a current source, and an emitter of the transistor Q1210 isgrounded via the resistor R1210. A collector of the transistor Q1205 isconnected to one end of the resistor R1206, and the other end of theresistor R1206 is connected to the supply line of the power supplyvoltage V_(CC) via the resistor R1203 and is connected to the base ofthe transistor Q1217. Further, a collector of Q1217 is connected to thesupply line of the power supply voltage V_(CC), an emitter is connectedto a collector of the transistor Q1221 serving as a current source, andan emitter of the transistor Q1221 is grounded via the resistor R1216. Acollector of the transistor Q1206 is connected to one end of theresistor R1207, and the other end of the resistor R1207 is connected tothe supply line of the power supply voltage V_(CC) via the resistorR1203 and is connected to a base of the transistor Q1216. Further, thecollector of Q1216 is connected to the supply line of the power supplyvoltage V_(CC), an emitter is connected to a collector of the transistorQ1220 serving as a current source, and an emitter of the transistorQ1220 is grounded via the resistor R1215. Further, a base of thetransistor Q1210 serving as a current source is connected to the supplyline of the control signal C1202, and bases of the transistors Q1220 andQ1221 similarly serving as current sources are connected to the supplyline of the control signal C1203.

The transistors Q1205, Q1206, Q1210, Q1216, Q1217, Q1220, and Q1221 andresistors R1203, R1206, R1207, R1210, R1215, and R1216 constitute thelow-level output stage operational amplifier OP123.

Further, the shift register 130 has flip-flops FF1301 to FF1303, aninverter 11301, and a buffer B1301 and performs phase shift processingon the 32 strings of waveform data “data0” to “data31” (D0 to D31) basedon the reference clock from the buffer 140.

In the present example, to process reliably a high frequency signal inthe P/S conversion circuit 70, as shown in FIG. 18, the 32 strings ofwaveform data “data0” to “data31” are divided into 16 strings each, thatis, D0 to D15 and D16 to D31, and signal processed by P/S conversion instates shifted in phase by ½ clock and 1 clock respectively. The shiftregister 130 shifts the phases of D0 to D15 and D16 to D31 differentlyand supplies the results to the selector 110.

FIGS. 19(A) to (L) are timing charts of the processing in the P/Sconversion circuit 70 generating these fine width pulses.

As shown in FIGS. 19(A) to (L), the P/S conversion circuit 70 obtainsthe difference of two adjacent phase shift pulses among the 32 types ofphase shift pulses CK0 to CK31 to prepare 32 fine width pulses of{fraction (1/32)} clock widths from the reference clock.

Then, it combines the 32 fine width pulses generated in this way to forma timing pulse and selectively combines.the fine width pulses inaccordance with the “H”s and “L”s of the parallel pulse signalscorresponding to the waveform data being sent from the decoder 40 so asto output a serial signal corresponding to the pulse waveform data.

In this way, in the present example, high-speed processing becomespossible by fine width pulses created from a reference clock andtherefore the load for speeding up a clock is lightened.

Next, the operation in FIG. 1 will be explained.

Note that, here, it is assumed that the RAM 30 stores waveform datacorresponding to the first strategy mode and the second strategy modebased on setting data of the mode register unit 10.

At the time of an ordinary recording operation, recording data (NRZI),for example, parallel data signals DT0 to DT5, is input to the addressencoder 20. The address encoder 20 converts the parallel data input atthe rising edge timing of the clock signal DCLK to serial data.

The address encoder 20 judges the recording data (2T˜≧8T or 2T˜≧4T)converted to serial data and generates a read address Radr of the RAM 30in which a pulse pattern corresponding to the mark length or spacelength indicated by the recording data is written. Then, the addressencoder 20 outputs this to the RAM 30 together with the generated readclock RCLK.

In this way, the RAM 30 searches through a memory area based on the readaddress received from the address encoder 20, reads out the pulsewaveform data corresponding to the mark length of the light source drivesignal, and outputs it to the decoder 40.

Further, the PLL circuit 50 controls the 16-tap ring oscillator 60 sothat for example a phase-synchronized clock signal of a frequency sixtimes the synchronization signal DCLK of the parallel signals DT0 to DT5being input to the address encoder 20 is generated at the oscillator 60.

The 16-tap ring oscillator 60 is controlled by the PLL circuit 50 andshifts the phase of the clock synchronized in phase with the referencesignal. Due to this, it generates 32 types of phase shift pulse signalsCK0 to CK31 shifted in phase by increments of {fraction (1/32)} (1/n) ofthe clock width from the reference clock RCLK by the differentialoutputs of the 16 taps. Then, it outputs these phase shift pulses CK0 toCK31 to the P/S conversion circuit 70.

The P/S conversion circuit 70 generates fine width pulses from the phasedifference of two phase shift pulses among the phase shift pulses CK0 toCK31 shifted by the oscillator 60 based on the two pulses. The P/Sconversion circuit 70 further converts the generated plurality of finewidth pulses to a serial pulse signal by serially adding the two-valuesignals of the parallel signals from the decoder 40 and outputs theresult to the output circuit 80.

Further, the output circuit 80 performs the necessary signal processingsuch as amplification or impedance matching on the serial signal fromthe P/S conversion circuit 70 and outputs the result to the light sourcedriver 90.

Further, the light source driver 90 drives the laser light source 100 inaccordance with the input signal.

In this way, the P/S conversion circuit of the, present example caneffectively convert fine width pulses obtained by a phase shift to aserial format without increasing the speed of the reference clock.Therefore, it becomes possible to realize a P/S conversion circuitfeaturing high speed and high accuracy processing without increasing thecomplexity of the circuit or the cost.

Further, by using such a P/S conversion circuit, it is possible toconfigure an optical recording apparatus controlling a laser driver foroptical disk recording and it is possible to contribute to higher speedoperation and higher accuracy of an optical disk apparatus improved inwrite strategy function.

Note that the above explanation was an example of the present invention.The concrete circuit configurations and values may be suitably modified.

Further, the shape of a light drive signal, the structure of thewaveform data, etc. are not limited to the above example. They may bewidely applied to various embodiments.

Further, the P/S conversion circuit is not limited in application to anoptical recording apparatus. It may also be widely used for otherelectronics apparatuses.

FIG. 20 is a circuit diagram of principal parts of an optical diskapparatus as an optical recording apparatus using a light output controlcircuit according to the present invention.

In FIG. 20, an optical disk apparatus 200 has an optical disk medium201, an optical pickup 202, a laser driver circuit (LDDRV) 203, and apulse signal generation circuit (PGEN) 204. The optical pickup 202 has alaser diode (LD) 100 which emits laser light LO in accordance with thevalue of a drive current to the optical disk medium 201, a monitoringuse photo detector (PD) 101 which receives the laser light LO emitted bythe LD 100 and generates a monitor current corresponding to the receivedlevel, and a photo detector 205 which receives the reflected returnlight RLO of the laser light LO emitted to the optical disk medium 201and generates a current of a value corresponding to the received levelas main components.

The laser driver circuit 203 corresponds to the light source driver 90in FIG. 1. The pulse signal generation circuit 204 includes the moderegister (MREG), address encoder (AENC) 20, RAM (waveform data memory)30, decoder (DEC) 40, PLL (Phase Locked Loop) circuit 50, 16-tap ringoscillator (OSC) 60 serving as a phase shifting means, parallel/serial(P/S) conversion circuit 70, and output circuit (OUTC) 80 of FIG. 1.

In this way, the light output control circuit 1 according to the presentinvention can be applied to an optical disk apparatus and enables ahigher speed and higher accuracy of the optical disk apparatus.

As explained above, according to the present invention, since the phaseof the reference clock pulse is shifted in increments of 1/n width ofthe pulse width, a fine width pulse is generated from a phase differencebetween two phase shift pulses among the phase shift pulses, the finewidth pulses are added serially corresponding to an input of parallelsignals, and a serial pulse signal is output, higher speed and higheraccuracy of P/S conversion can be realized at a low cost without using asuper high-speed clock.

Further, according to the present invention, when receiving as inputparallel signals based on waveform data read from a waveform data memorycorresponding to mark lengths to be recorded on the optical recordingmedium, converting these parallel signals to a serial signal by aparallel/serial conversion circuit, since the phase of the referenceclock pulse is shifted in increments of 1/n width of the pulse width, afine width pulse is generated from a phase difference between two phaseshift pulses among the phase shift pulses, the fine width pulses areadded serially corresponding to an input of parallel signals, and aserial pulse signal is output, higher speed and higher accuracy of P/Sconversion can be realized at a low cost without using a superhigh-speed clock and waveform control of a pulse signal be output to thelight source driver can be optimized for high speed and high accuracy.

Industrial Applicability

According to the parallel/serial conversion circuit, light outputcontrol circuit, and optical recording apparatus of the presentinvention, higher speed and higher accuracy of P/S conversion can berealized at a low cost without using a super high-speed clock andwaveform control of a pulse signal being output to the light sourcedriver can be optimized for high speed and high accuracy, so the presentinvention is suitable for an optical disk apparatus such as a phasechange type optical disk and can be widely used for other electronicsapparatuses.

What is claimed is:
 1. A parallel/serial conversion circuit forconverting parallel signals input to a serial pulse signal andoutputting the same, comprising: a phase shifting means for shifting aphase of a reference clock pulse by increments of 1/n width of a pulsewidth, a fine width pulse generating means for receiving as input twophase shift pulses among the phase shift pulses shifted by the phaseshifting means and generating a fine width pulse from a phase differencebetween the two, and a serial signal generating means for seriallyadding the fine width pulses generated by said fine width pulsegenerating means corresponding to said parallel signal input andoutputting a serial pulse signal.
 2. A parallel/serial conversioncircuit as set forth in claim 1, wherein said fine width pulsegenerating means generates said fine width pulse from two adjacent phaseshift pulses among the phase shifted pulses shifted by said phaseshifting means.
 3. A parallel/serial conversion circuit as set forth inclaim 1, wherein the circuit comprises a changing means for receiving asinput two adjacent phase shift pulses among the phase shift pulsesshifted by said phase shifting means and changing their levels todifferent levels, and said fine width pulse generating means generatessaid fine width pulse from the two phase shift pulses changed in levelby said level changing means.
 4. A parallel/serial conversion circuit asset forth in claim 1, wherein said phase shifting means includes a ringoscillator connecting a plurality of cells in a ring.
 5. Aparallel/serial conversion circuit as set forth in claim 1, wherein:said phase shifting means includes a ring oscillator connecting aplurality of delay cells in a ring, and said plurality of delay cellsare laid out so as to make delays cells which become odd-numbered stagesand even-numbered stages when connected in a ring face each other and sothat interconnects which connect them become approximately equal.
 6. Alight output control circuit which controls a light output of a lightsource for emitting predetermined data light to an optical medium,comprising: a light source driver for driving the light source inresponse to said serial pulse signal and a parallel/serial conversioncircuit for receiving as input parallel signals based on waveform datacorresponding to data light to be emitted by said light source,converting said parallel signals to a serial pulse signal, andoutputting the same to said light source driver, said parallel/serialconversion circuit comprising: a phase shifting means for shifting aphase of a reference clock pulse by increments of 1/n width of a pulsewidth, a fine width pulse generating means for receiving as input twophase shift pulses among the phase shift pulses shifted by the phaseshifting means and generating a fine width pulse from a phase differencebetween the two, and a serial signal generating means for seriallyadding the fine width pulses generated by said fine width pulsegenerating means corresponding to said parallel signal input andoutputting a serial pulse signal.
 7. A light output control circuit asset forth in claim 6, further comprising: a waveform data memory forstoring waveform data corresponding to data to be emitted by the lightsource, an accessing means for receiving as input the data to be emittedby the light source, judging the address of the waveform data memorycorresponding to the input data, and accessing said waveform datamemory, and a decoding means for decoding the waveform data read fromthe waveform data memory by said accessing means and outputting parallelsignals which indicate the pulse waveform data to a parallel/serialconversion circuit.
 8. A light output control circuit as set forth inclaim 6, wherein said fine width pulse generating means generates saidfine width pulse from two adjacent phase shift pulses among the phaseshifted pulses shifted by said phase shifting means.
 9. A light outputcontrol circuit as set forth in claim 6, wherein: the circuit comprisesa changing means for receiving as input two adjacent phase shift pulsesamong the phase shift pulses shifted by said phase shifting means andchanging their levels to different levels, and said fine width pulsegenerating means generates said fine width pulse from the two phaseshift pulses changed in level by said level changing means.
 10. A lightoutput control circuit as set forth in claim 6, wherein said phaseshifting means includes a ring oscillator connecting a plurality ofcells in a ring.
 11. A light output control circuit as set forth inclaim 6, wherein: said phase shifting means includes a ring oscillatorconnecting a plurality of delay cells in a ring, and said plurality ofdelay cells are laid out so as to make delays cells which becomeodd-numbered stages and even-numbered stages when connected in a ringface each other and so that interconnects which connect them becomeapproximately equal.
 12. An optical recording apparatus for outputting alight source drive signal to a light source driver which writes data toan optical recording medium based on recording data indicating a lengthof a mark to be recorded on said optical recording medium, comprising: aparallel/serial conversion circuit for receiving as input parallelsignals based on waveform data read from a waveform data memorycorresponding to a length of a mark recorded on the optical recordingmedium, converting said parallel signals to a serial pulse signal, andoutputting the same to said light source driver, said parallel/serialconversion circuit comprising: a phase shifting means for shifting aphase of a reference clock pulse by increments of 1/n width of the pulsewidth, a fine width pulse generating means for receiving as input twophase shift pulses among said phase shift pulses shifted by said phaseshifting means and generating a fine width pulse based on a phasedifference between the two, and a serial signal generating means forserially adding the fine width pulses generated by said fine width pulsegenerating corresponding to said parallel signal input and outputting aserial pulse signal.
 13. An optical recording apparatus as set forth inclaim 12, further comprising: a waveform data memory for storingwaveform data corresponding to data to be emitted by the light source,an accessing means for receiving as input the data to be emitted by thelight source, judging the address of the waveform data memorycorresponding to the input data, and accessing said waveform datamemory, and a decoding means for decoding the waveform data read fromthe waveform data memory by said accessing means and outputting parallelsignals which indicate the pulse waveform data to a parallel/serialconversion circuit.
 14. An optical recording apparatus as set forth inclaim 12, wherein said fine width pulse generating means generates saidfine width pulse from two adjacent phase shift pulses among the phaseshifted pulses shifted by said phase shifting means.
 15. An opticalrecording apparatus as set forth in claim 12, wherein: the circuitcomprises a changing means for receiving as input two adjacent phaseshift pulses among the phase shift pulses shifted by said phase shiftingmeans and changing their levels to different levels, and said fine widthpulse generating means generates said fine width pulse from the twophase shift pulses changed in level by said level changing means.